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ZL9117M
using an external reset controller to control external digital logic.
By default, the ZL9117M PG delay is set equal to the soft-start
ramp time setting. Therefore, if the soft-start ramp time is set to
10ms, the PG delay is set to 10ms. The PG delay may be set
independently of the soft-start ramp using the I 2 C/SMBus as
described in Application Note AN2033 .
Switching Frequency and PLL
The ZL9117M incorporates an internal phase-locked loop (PLL) to
clock the internal circuitry. The PLL can be driven by an external
clock source connected to the SYNC pin. When using the internal
oscillator, the SYNC pin can be configured as a clock source.
The internal switching frequency of the ZL9117M is 571kHz.
Loop Compensation
The ZL9117M operates as a voltage-mode synchronous buck
controller with a fixed frequency PWM scheme. The module is
internally compensated via the I 2 C/SMBus interface.
The ZL9117M has an auto compensation feature that measures
the characteristics of the power train and calculates the proper
tap coefficients. By default, auto compensation is configured to
execute one time after ramp with 50% auto compensation Gain
with Power-Good asserted immediately after the first auto
compensation cycle completes.
Please refer to Application Note AN2033 for further details.
Adaptive Diode Emulation
Adaptive diode emulation mode turns off the low-side FET gate
drive at low load currents to prevent the inductor current from
going negative, reducing the energy losses and increasing overall
efficiency. Diode emulation is available to single-phase devices
only.
Note: the overall bandwidth of the device may be reduced when
in diode emulation mode. Disabling the diode emulation prior to
applying significant load steps is recommended.
Input Undervoltage Lockout
The input undervoltage lockout (UVLO) prevents the ZL9117M
from operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The UVLO
threshold (V UVLO ) can be set between 2.85V and 16V using the
I 2 C/SMBus interface.
Once an input undervoltage fault condition occurs, the device
can respond in a number of ways, as follows:
1. Continue operating without interruption.
2. Continue operating for a given delay period, followed by
shutdown if the fault still exists. The device remains in
shutdown until instructed to restart.
3. Initiate an immediate shutdown until the fault is cleared. The
user can select a specific number of retry attempts.
The default response from a UVLO fault is an immediate
shutdown of the module. The controller continuously checks for
the presence of the fault condition. If the fault condition is no
longer present, the ZL9117M is re-enabled.
11
Please refer to Application Note AN2033 for details on how to
configure the UVLO threshold or to select specific UVLO fault
response options via the I 2 C/SMBus interface.
Output Overvoltage Protection
The ZL9117M offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry from
being subjected to a voltage higher than its prescribed limits. A
hardware comparator is used to compare the actual output
voltage (seen at the FB+ pin) to a threshold set to 15% higher
than the target output voltage (the default setting). If the FB+
voltage exceeds this threshold, the PG pin de-asserts, and the
controller can then respond in a number of ways, as follows:
1. Initiate an immediate shutdown until the fault is cleared. The
user can select a specific number of retry attempts.
2. Turn off the high-side MOSFET and turn on the low-side
MOSFET. The low-side MOSFET remains ON until the device
attempts a restart.
The default response from an overvoltage fault is to immediately
shut down. The controller continuously checks for the presence
of the fault condition, and when the fault condition no longer
exists, the device is re-enabled.
For continuous overvoltage protection when operating from an
external clock, the only allowed response is an immediate
shutdown.
Please refer to Application Note AN2033 for details on how to
select specific overvoltage fault response options via I 2 C/SMBus.
Output Pre-Bias Protection
An output pre-bias condition exists when an externally applied
voltage is present on a power supply’s output before the power
supply’s control IC is enabled. Certain applications require that
the converter not be allowed to sink current during start-up if a
pre-bias condition exists at the output. The ZL9117M provides
pre-bias protection by sampling the output voltage prior to
initiating an output ramp.
If a pre-bias voltage lower than the target voltage exists after the
pre-configured delay period has expired, the target voltage is set
to match the existing pre-bias voltage, and both drivers are
enabled. The output voltage is then ramped to the final
regulation value at the preconfigured ramp rate.
The actual time the output takes to ramp from the pre-bias
voltage to the target voltage varies, depending on the pre-bias
voltage, however, the total time elapsed from when the delay
period expires and when the output reaches its target value will
match the pre-configured ramp time. See Figure 13.
FN7914.3
July 22, 2013
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